View CY2X0137FLXCT_8320970.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy2x0137 high performance lvds oscillator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-86061 rev. *a revised october 30, 2013 high performance lvds oscillator features low jitter crystal oscillator (xo) less than 1 ps typical root mean square (rms) phase jitter low-voltage differential signaling (lvds) output output frequency from 50 mhz to 690 mhz factory-configured or field-programmable integrated phase-locked loop (pll) can be configured as four different type devices supply voltage: 3.3 v or 2.5 v pb-free package: 7.0 5.0 mm leadless chip carrier (lcc) commercial and industrial temperature ranges functional description the cy2x0137 is a high-performance and high-frequency xo. the device uses a cypress proprietary low-noise pll to synthesize the frequency from an integrated crystal. the cy2x0137 is available as a factory-configured device or as a field-programmable device. fa ctory-configured devices are configured for general use or they can be customer-specific. the same cy2x0137 can be configured as four different device type as mentioned in logic block diagram.
cy2x0137 document number: 001-86061 rev. *a page 2 of 20 logic block diagram programmable configuration output divider 1 6 3 v dd v ss oe/pd# crystal oscillator low- noise pll 4 clk 5 clk# programmable configuration output divider 1 sda crystal oscillator low-noise pll 4 clk 5 clk# 2 scl i 2 c interface output divider 1 fs1 crystal oscillator low-noise pll 4 clk 5 clk# 2 fs0 frequency select decode programmable configuration outp ut divider 2 6 3 vdd vss oe/pd# crystal oscillator 4clk 5clk# 1 vin low-noise pll device type 1: high performance lvds crystal oscillator with output enable device type 2: high performance lvds crystal oscillator with frequency margining - i2c control device type 3: high performance lvds crystal oscillator with frequency margining - frequency select device type 4: high performance lvds voltage controlled crystal oscillator
cy2x0137 document number: 001-86061 rev. *a page 3 of 20 contents pinouts .............................................................................. 4 pin definitions .................................................................. 4 functional description ..................................................... 5 device type 1 ............................................................. 5 device type 2 ............................................................. 5 device type 3 ............................................................. 5 device type 4 ............................................................. 5 programming description ............................................... 6 field programmable cy2x0137f ............................... 6 factory configured cy2x0137 ................................... 6 programming variables ................................................... 6 output frequency ........................................................ 6 pin 1: output enable (oe) or power-down (pd#) ...... 6 industrial versus commercial device performance .... 6 absolute pull range ............ .............. .............. ............ 6 memory map ...................................................................... 7 serial interface protocol and timing ........................... 7 device address ........................................................... 7 data valid .................................................................... 7 data frame ................................................................. 7 acknowledge pulse ..................................................... 7 write operations ............................................................... 8 writing individual bytes ....... .............. .............. ............ 8 writing multiple bytes .................................................. 8 read operations ............................................................... 8 current address read ................................................. 8 random read .............. .............. .............. ............ ....... 8 sequential read .......................................................... 8 absolute maximum conditions ..................................... 11 operating conditions ..................................................... 11 dc electrical characteristics ........................................ 12 ac electrical characteristics ........................................ 13 switching waveforms .................................................... 14 termination circuits ....................................................... 15 ordering information ...................................................... 16 possible configurations ............................................. 16 ordering code definitions ..... .................................... 16 package diagram ............................................................ 17 acronyms ........................................................................ 18 document conventions ................................................. 18 units of measure ....................................................... 18 document history page ................................................. 19 sales, solutions, and legal information ...................... 20 worldwide sales and design s upport ......... .............. 20 products .................................................................... 20 psoc? solutions ...................................................... 20 cypress developer community ................................. 20 technical support ................. .................................... 20
cy2x0137 document number: 001-86061 rev. *a page 4 of 20 pinouts figure 1. 6-pin ceramic lcc pinout 1 3 oe/pd# v ss v dd clk 6 4 2 5clk# dnu 1 3 sda v ss v dd clk 6 4 2 5clk# sclk 1 3 fs1 vss vdd clk 6 4 2 5clk# fs0 1 3 vin vss vdd clk 6 4 2 5clk# oe/pd# device type 1: high performance lvds crystal oscillator with output enable: device type 2: high performance lvds crystal oscillator with frequency margining - i2c control device type 3: high performance lvds crystal oscillator with frequency margining - frequency select device type 4: high performance lvds voltage controlled crystal oscillator pin definitions 6-pin ceramic lcc name device type 1 device type 2 device type 3 device type 4 i/o type description oe/pd# 1 n/a n/a 2 cmos input output enable pin: active high. if oe = 1, clk is enabled. power-down pin: active low. if pd# = 0, the device is powered down and the clock is disabled. the functionality of this pin is programmable clk, clk# 4,5 4,5 4,5 4,5 lvds output differential output clock dnu 2 n/a n/a n/a ? do not use: dnu pins are electrically connected, but perform no function v dd 6 6 6 6 power supply voltage: 2.5 v or 3.3 v v ss 3 3 3 3 power ground fs1, fs0 n/a n/a 1,2 n/a cmos input frequency select sda n/a 1 n/a n/a i/o i2c serial data sclk n/a 2 n/a n/a cmos input i2c serial clock vin n/a n/a n/a 1 analog input vcxo control voltage, positive slope
cy2x0137 document number: 001-86061 rev. *a page 5 of 20 functional description device type 1 device type 1 is a simple crystal oscillator with one output frequency. pin 1 can be programmed either as oe or pd#. the oe function is used to enable or disable the clk output whereas pd# function puts the device into a low-power state, device type 2 in device type 2, it has an i 2 c bus serial interface [1] , which is used to change the output frequency. the cy2x0137 comes configured for four different frequencies. at power-on, the four configur ations are transparently loaded into an internal volatile memory which, in turn, controls the pll. the user can switch between th e four frequencies through the i 2 c bus. the user can also configure the cy2x0137 with new output frequencies by shifting new data into the internal memory. frequency margining is a common application for this feature. one frequency is used for the standard operating mode of the device, while additional frequencies are available for margin testing, either during produ ct development or in-system manufacturing test. note that all configuration changes made using i 2 c are temporary and are lost when power is removed from the device. at power-on, the device returns to its original state. the configuration for a particular frequency is stored in a 6-byte block of memory, known as a word. the cy2x0137 has four such words, labeled ?frequency word 0? through ?frequency word 3?. an additional register byte contains a 2-bit field, which selects one of the four frequency wo rds. by writing to this select byte, the user can switch back and forth between the four programmed frequencies. the select byte can be configured to select any of the four frequency words at power-on. when changing the output frequ ency, the frequency transition is not guaranteed to be smooth. there can be frequency excursions beyond the start fr equency and the new frequency glitches and runt pulses are poss ible, and time must be allowed for the pll to re-lock. if more than four frequencies are needed, the i 2 c bus can be used to change any of the four frequency words. when writing frequency words through i 2 c, the users should not change the currently selected word. instead, write one of the three unselected words before changing the select byte to select that new word. figure 2 shows how the frequency words are arranged and selected. figure 2. frequency words device type 3 the fs0 and fs1 pins select between four different output frequencies, as shown in table 1 . frequency margining is a common application for this feat ure. one frequency is used for the standard operating mode of the device, while the other frequencies are available for margin testing, either during product development or in system manufacturing test. when changing the output frequ ency, the frequency transition is not guaranteed to be smooth. there can be frequency excursions beyond the start frequency and the new frequency. glitches and runt pulses are possible, and time must be allowed for the pll to relock. device type 4 device type 4 is a voltage controlled crystal oscillator. it has a control voltage pin vin which is an analog input that is used to adjust the output frequency. the nominal output frequency is defined when vin = v dd,nom /2. increasing the voltage on vin increases the output frequency, while decreasing the voltage on vin decreases the output freq uency. any voltage between v ss and v dd is allowed on vin. the voltage or frequency slope is very linear over most of the control voltage range. table 1. frequency select fs1 fs0 output frequency 0 0 frequency 0 0 1 frequency 1 1 0 frequency 2 1 1 frequency 3 10h ? 15h frequency word 0 pll frequency word 1 frequency word 2 frequency word 3 16h ? 1bh 1ch ? 21h 22h ? 27h select byte 40h 00 01 10 11 bits [1:0] register address sel control note 1. the serial interface is i 2 c bus compliant, with the following exceptions: sda input leakage cu rrent, sda input capacitance, sda and sclk are clamped to v dd , setup time, and output hold time.
cy2x0137 document number: 001-86061 rev. *a page 6 of 20 programming description the cy2x0137 is a programmable device. prior to being used in an application, it must be programmed with the output frequency and other variables described in programming variables . two different device types are available, each with its own programming flow. they are described in the following sections. field programmable cy2x0137f field programmable devices are shipped unprogrammed and must be programmed before being installed on a pcb. customers use cyclockwizard? software to specify the device configuration and generate a joint electron devices engineering council (jedec - extension .jed) programming file. programming of samples and prototype quantities is available using the cyclockwizard software along with a cy3675-clkmaker1 cyclockmaker clock programmer kit and cy3675-lcc6b socket adapter. cypress?s value-added distribution partners also provide programming services. field-programmable devices are designated with an ?f? in the part number. they are in tended for quick prototyping and inventory reduction. jedec fo r these four devices can be generated using cyclockwizard 1.0. however while creating jedec or programming different device types, different mpns has to be selected in the cyclockwizard 1.0 software. please see table below. you can download the software and programmer kit hardware from www.cypress.com by clicking the hyperlinks in the previous paragraph. factory configured cy2x0137 for ready-to-use devices, the cy2x0137 is available with no field programming required. pre-configured devices are available for samples or orders, or a request for a custom configuration can be made. all requests are submitted to the local cypress field application engineer (fae) or sales representative. after the request is processed, the user receives a new part number, samples, and datasheet with the programmed values. this part number is used for additional sample requests and production orders. the cy2x0137 is one-time programmable (otp). programming variables output frequency the cy2x0137 can synthesize a frequency to a resolution of one part per million (ppm), but the actual accuracy of the output frequency is limited by the accuracy of the integrated reference crystal. the cy2x0137 has an output frequency range of 50 mhz to 690 mhz, but the range is not continuous. the cy2x0137 cannot generate frequencies in the ranges of 521 mhz to 529 mhz and 596 mhz to 617 mhz. pin 1: output enable (oe) or power-down (pd#) this function is only available in device type 1 and 4. pin 1 (device type 1) or pin 2 (device type 2) is programmed as either oe or pd#. the oe function is used to enable or disable the clk output quickly, but it does not reduce core power consumption. the pd# function puts the device into a low-power state, but the wake-up takes longer because the pll must reacquire the lock. industrial versus commerc ial device performance industrial and commercial devices have different internal crystals. they have a potentia lly significant impact on performance levels for applicati ons requiring the lowest possible phase noise. cyclockwizard 1.0 software allows the user to select between and view the expected performance of both options. absolute pull range this is only applicable for device type 4. the pull range of the vcxo, measured in parts per million (ppm) is programmable. the configuration software allows the user to select one of seven possible absolute pull ranges (apr), ranging up to approximately 200 ppm. apr is the net pull range of the device, after subtracting frequency variability due to device variation, and temperature, voltage and aging effects. table 2. mpns selection on cyclockwizard 1.0 software device type mpn selection on cyclockwizard 1.0 device type 1 cy2x013 device type 2 cy2xf23 device type 3 cy2xf33 device type 3 contact local cypress fae table 3. device programming variables variable device type output frequency device type 1 and 4 pin 1 function (oe or pd#) device type 1 temperature range (commercial or industrial) device type 1, 2, 3 and 4 output frequency 0 device type 2 and 3 output frequency 1 device type 2 and 3 output frequency 2 device type 2 and 3 output frequency 3 device type 2 and 3 absolute pull range device type 4 pin 2 function (oe or pd#) device type 4
cy2x0137 document number: 001-86061 rev. *a page 7 of 20 memory map five fields can be written via the i 2 c bus. four frequency words define the output frequency. as shown in ta b l e 4 , each of these words is a 6-byte field. when writing to a frequency word, all six bytes should be written. they may be written either as individual byte writes, or as a block writ e. the currently selected frequency word should not be written to. all four words are symmetrical, meaning that a 6-byte value that is valid for one word is also valid for any of the other words, and produces the same frequency. the fifth field is the select byte, located at byte address 40h. the value written into the two least significant bits determines the active frequency word. the other bits of the byte are reserved and must be written with the values indicated in the table. users should never write to any address other than the 25 bytes described here. serial interface protocol and timing the cy2x0137 uses pins sda and sclk for an i 2 c bus that operates up to 100 kbits/sec in read or write mode. the cy2x0137 is always a slave on this bus, meaning that it never initiates a bus transaction. the basic write protocol is as follows: start bit; 7-bit device address (da); r/w bit; slave clock acknowledge (ack); 8-bit memory address (ma); ack; 8-bit data; ack; 8-bit data in ma+1 if desired; ack; 8-bit data in ma+2; ack; and so on, until stop bit. the basic serial format is illustrated in figure 4 on page 9. device address the device i 2 c address is a 7-bit value. the default i 2 c address, which appears in cyclockwizard is 69h, which can be changed to any other value while generating configuration using cyclockwizard . note that the field programmable (unprogrammed [2] ) devices has default address as 59h. data valid data is valid when the clock is high, and may only be transitioned when the clock is low as illustrated in figure 5 on page 9. data frame every new data frame is indicated by a start and stop sequence, as illustrated in figure 6 on page 9. start sequence - start frame is indicated by sda going low when sclk is high. every time a start signal is given, the next 8-bit data must be the device address (seven bits) and a r/w bit, followed by register address (eight bits) and register data (eight bits). stop sequence - stop frame is indicated by sda going high when sclk is high. a stop frame frees the bus for writing to another part on the same bus or writing to another random register address. acknowledge pulse during write mode, the cy2x0137 responds with an acknowledge (ack) pulse after every eight bits. this is accomplished by pulling the sda line low during the n*9 th clock cycle as illustrated in figure 7 on page 10. (n = the number of bytes transmitted). after the dat a packet is sent during read mode, the master generates the acknowledge. table 4. frequency words frequency word byte addresses (hex) word select (select byte 40h) 0 10h to 15h 00 1 16h to 1bh 01 2 1ch to 21h 10 3 22h to 27h 11 table 5. register 40h: select byte bits default value (binary) name description 7:2 000000 reserved reserved. always write this value. 1:0 user-defined word select selects the frequency word to determine the output frequency. 00 selects word 0; 01 selects word 1; 10 selects word 2; 11 selects word 3. note 2. field programmable devices are shipped unprogrammed and must be programmed before being installed on a pcb. an unprogrammed d evice will output the crystal frequency of the integrated crystal (25 mhz for commercial and 38.8 mhz for industrial).
cy2x0137 document number: 001-86061 rev. *a page 8 of 20 write operations writing individual bytes a valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (sda = 0/low). the next eight bits must contain the data word intended for storage. after the data word is received, the slave responds with another acknowledge bit (sda = 0/low), and the master must end the write sequence with a stop condition. writing multiple bytes to write more than one byte at a time, the master does not end the write sequence with a stop cond ition. instead, the master can send multiple contiguous bytes of data to be stored. after each byte, the slave responds with an acknowledge bit, just like after the first byte, and accepts data until the acknowledge bit is responded to by the stop condition. when receiving multiple bytes, the cy2x0137 internally increments the register address. read operations read operations are initiated t he same way as write operations except that the r/w bi t of the slave address is set to ?1? (high). there are three basic read operations: current address read, random read, and sequential read. current address read the cy2x0137 has an onboard address counter that retains 1 more than the address of the last word access. if the last word written or read was word ?n?, then a current address read operation would return the value stored in location ?n+1?. when the cy2x0137 receives the slave address with the r/w bit set to a ?1?, the cy2x0137 issues an acknowledge and transmits the 8-bit word. the master device does not acknowledge the transfer, but does generate a st op condition, which causes the cy2x0137 to stop transmission. random read through random read operations, the master may access any memory location. to perform this ty pe of read operation, first the word address must be set. this is accomplished by sending the address to the cy2x0137 as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. next the master reissues the control byte with the r/w byte set to ?1?. the cy2x0137 then issues an acknowledge and transmits the 8-bit word. the master device does not acknowledge the transfer, but does generate a stop condition which causes the cy2x0137 to stop transmission. sequential read sequential read operations follow the same process as random reads except that the master i ssues an acknowledge instead of a stop condition after transmission of the first 8-bit data word. this action results in an incrementing of the internal address pointer, and subsequently output of the next 8-bit data word. by continuing to issue acknowledges instead of stop conditions, the master may serially read t he entire contents of the slave device memory. when the internal address pointer points to the ffh register, after the next increm ent, the pointer will point to the 00h register. figure 3. data transfer sequence on the serial bus sclk start condition sda stop data may address or acknowledge valid be changed condition
cy2x0137 document number: 001-86061 rev. *a page 9 of 20 figure 4. data frame architecture figure 5. data valid and data transition periods figure 6. start and stop frame sda write start signal device address 7-bit r/w = 0 1 bit 8-bit register address slave 1 bit ack slave 1 bit ack 8-bit register data stop signal multiple contiguous registers slave 1 bit ack 8-bit register data (xxh) (xxh) (xxh+1) slave 1 bit ack 8-bit register data (xxh+2) slave 1 bit ack 8-bit register data (ffh) slave 1 bit ack 8-bit register data (00h) slave 1 bit ack slave 1 bit ack sda read start signal device address 7-bit r/w = 1 1 bit 8-bit register data slave 1 bit ack slave 1 bit ack stop signal sda read start signal device address 7-bit r/w = 0 1 bit 8-bit register address slave 1 bit ack slave 1 bit ack 7-bit device stop signal multiple contiguous registers master 1 bit ack 8-bit register data master 1 bit ack (xxh) (xxh) master 1 bit ack 8-bit register data (xxh+1) master 1 bit ack 8-bit register data (ffh) master 1 bit ack 8-bit register data (00h) master 1 bit ack master 1 bit ack current address read address +r/w=1 repeated start bit sda sclk data valid transition to next bit clk low clk high vih vil t su t dh sda sclk start transition to next bit stop
cy2x0137 document number: 001-86061 rev. *a page 10 of 20 figure 7. frame format (device address, r/w , register address, register data) sda sclk da6 da5 da0 r/w ack ra7 ra6 ra1 ra0 ack stop start ack d7 d6 d1 d0 +++ + + +
cy2x0137 document number: 001-86061 rev. *a page 11 of 20 absolute maximum conditions parameter description condition min max unit v dd supply voltage ?0.5 4.4 v v in [3] input voltage, dc relative to v ss ?0.5 v dd + 0.5 v t s temperature, storage non operating ?55 135 c t j temperature, junction ?40 135 c esd hbm electrostatic discharge (esd) protection human body model (hbm) jedec std 22-a114-b 2000 ? v ? ja [4] thermal resistance, junction to ambient 0 m/s airflow 64 c / w operating conditions parameter description min typ max unit v dd 3.3 v supply voltage range 3.0 3.3 3.6 v 2.5 v supply voltage range 2.375 2.5 2.625 v t pu power-up time for v dd to reach minimum specified voltage (power ramp is monotonic) 0.05 ? 500 ms t a ambient temperature (commercial) 0 ? 70 c ambient temperature (industrial) ?40 ? 85 c notes 3. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 4. simulated. the board is derived from the jedec multilayer standard. it measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). the internal layers are 100% copper planes, while the top and bottom layers hav e 50% metalization. no vias are included in the model.
cy2x0137 document number: 001-86061 rev. *a page 12 of 20 dc electrical characteristics parameter description condition min typ max unit i dd [5] operating supply current v dd = 3.6 v, oe/pd# = v dd , output terminated, device type 1 and 4 ??125 ma v dd = 2.625 v, oe/pd# = v dd , output terminated, device type 1 and 4 ??120 ma v dd = 3.465 v, clk = 150 mhz, output terminated, device type 2 and 3 ??120ma v dd = 2.625 v, clk = 150 mhz, output terminated, device type 2 and 3 ??115ma i sb standby supply current pd# = v ss ??200 ? a v od lvds differential output voltage v dd = 3.3 v or 2.5 v, r term = 100 ? between clk and clk# 247 ? 454 mv ? v od change in v od between complementary output states v dd = 3.3 v or 2.5 v, r term = 100 ? between clk and clk# ??50 mv v os lvds offset output voltage v dd = 3.3 v or 2.5 v, r term = 100 ? between clk and clk# 1.125 ? 1.375 v ? v os change in v os between complementary output states v dd = 3.3 v or 2.5 v, r term = 100 ? between clk and clk# ??50 mv v ols output low voltage (sda) i ol = 4 ma ? ? 0.1 v dd v i oz lvds output leakage current tri- state output, unterminated, measured on one pin while floating the other pin, pd#/oe = v ss ?35 ? 35 ? a v ih input high voltage 0.7 v dd ?? v v il input low voltage ? ? 0.3 v dd v i ih0 input high current, pin 1 input = v dd ??115 ? a i ih1 input high current, pin 2 input = v dd ??10 ? a i il0 input low current, pin 1 input = v ss ?50 ? ? a i il1 input low current, pin 2 input = v ss ?20 ? ? ? a c in0 [6] input capacitance, pin 1 ?15?pf c in1 [6] input capacitance, pin 2 ? 4 ? pf v vin vin input voltage (device type 4) 0?v dd v i vin vin input current (device type 4) v ss ? vin ? v dd ?50 ? 115 ? a inl vin [6, 7] vin to f out integral nonlinearity (device type 4) v ss ? vin ? v dd ?1?% notes 5. i dd includes ~4 ma of current that is dissipated externally in the output termination resistors. 6. not 100% tested, guaranteed by design and characterization. 7. integral nonlinearity is defined in ieee standard 1241-2000.
cy2x0137 document number: 001-86061 rev. *a page 13 of 20 ac electrical characteristics the following table lists the ac electrical specifications for this device. [8] parameter description condition min typ max unit f out output frequency [9] 50 ? 690 mhz fsc frequency stability, commercial devices [10] v dd = min to max, t a = 0 c to 70 c ? ? 35 ppm fsi frequency stability, industrial devices [10] v dd = min to max, t a = ?40 c to 85 c ? ? 55 ppm ag aging, 10 years ? ? 15 ppm t dc output duty cycle f < 450 mhz, measured at zero crossing 45 50 55 % f > 450 mhz, measured at zero crossing 40 50 60 % t r , t f output rise and fall time 20% and 80% of full output swing ? 0.35 1.0 ns t ohz output disable time time from falling edge on oe to stopped outputs (asynchronous) ? ? 100 ns t oe output enable time time from rising edge on oe to outputs at a valid frequency (asynchronous) ? ? 120 ns t lock startup time time for clk to reach valid frequency measured from the time v dd = v dd (min) or from pd# rising edge ? ? 5 ms t lser relock time time for clk to reach valid frequency from serial bus change to select bits in register 40h, measured from i 2 c stop (device type 2) or time for clk to reach valid frequency from fs0 or fs1 pin change (device type 3) ? ? 1 ms t jitter( ? ) rms phase jitter (random) f out = 106.25 mhz (12 khz to 20 mhz) ? 1 ? ps notes 8. not 100% tested, guaranteed by design and characterization. 9. this parameter is specified in the cyclockwizard 1.0 software. 10. frequency stability is the maximum variation in frequency from f 0 . it includes initial accuracy, and variation from temperature and supply voltage.
cy2x0137 document number: 001-86061 rev. *a page 14 of 20 switching waveforms figure 8. output voltage swing figure 9. output offset voltage figure 10. duty cycle timing figure 11. output rise and fall time figure 12. output enable and disable timing clk clk# v od2 v od1 ? v od = v od1 - v od2 clk 50 ? clk# 50 ? v os clk t pw t period t dc = t pw t period clk# 20% 80% t r clk 20% 80% clk# t f oe clk high-impedance t ohz t oe v il v ih clk#
cy2x0137 document number: 001-86061 rev. *a page 15 of 20 termination circuits figure 13. lvds termination clk clk# 100 ?
cy2x0137 document number: 001-86061 rev. *a page 16 of 20 some product offerings are factory programmed customer specific devices with cust omized part numbers. the possible configurations table shows the available device types, but not complete part numbers. contact your local cypress fae or sales representative for more information. ordering code definitions ordering information part number configuration package description product flow pb-free CY2X0137FLXCT field-programmable 6-pin ceramic lcc smd - tape and reel commercial, 0 c to 70 c cy2x0137flxit field-programmable 6-pin ceramic lcc smd - tape and reel industrial, ?40 c to 85 c possible configurations part number [11] configuration package description product flow pb-free cy2x0137lxcxxx factory-configured 6-pin ceramic lcc smd commercial, 0 c to 70 c cy2x0137lxcxxxt factory-configured 6-pin ceramic lcc smd - tape and reel commercial, 0 c to 70 c cy2x0137lxixxx factory-configured 6-pin ceramic lcc smd industrial, ?40 c to 85 c cy2x0137lxixxxt factory-configured 6-pin ceramic lcc smd - tape and reel industrial, ?40 c to 85 c x = blank or t blank = tube; t = tape and reel customer part configuration code temperature range: x = c or i c = commercial; i = industrial pb-free package type: l = 6-pin ceramic lcc smd configuration: x = f or blank f = field programmable; blank = factory configured part identifier family company id: cy = cypress 2x cy 0137 x l xxx x x x notes 11. ?xxx? indicates factory programmed parts based on customer s pecific configuration. for more details, contact your local cypr ess fae or a sales representative.
cy2x0137 document number: 001-86061 rev. *a page 17 of 20 package diagram figure 14. 6-pin ceramic lcc (5.0 7. 0 1.80 mm) lz06b package outline, 001-85862 001-85862 *a
cy2x0137 document number: 001-86061 rev. *a page 18 of 20 acronyms document conventions units of measure acronym description esd electrostatic discharge fae field application engineer hbm human body model jedec joint electron devices engineering council lcc leadless chip carrier lvds low-voltage differential signaling oe output enable otp one-time programmable pcb printed circuit board pll phase-locked loop rms root mean square xo crystal oscillator symbol unit of measure c degree celsius mhz megahertz ? a microampere ma milliampere mv millivolt ms millisecond ns nanosecond ? ohm ppm parts per million pf picofarad ps picosecond v volt w watt
cy2x0137 document number: 001-86061 rev. *a page 19 of 20 document history page document title: cy2x0137, high performance lvds oscillator document number: 001-86061 revision ecn orig. of change submission date description of change ** 3944886 puru 06/21/2013 new data sheet. *a 4178429 cinm 10/30/2013 changed stat us from preliminary to final. updated ordering information (updated part numbers). updated in new template.
document number: 001-86061 rev. *a revised october 30, 2013 page 20 of 20 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2x0137 ? cypress semiconductor corporation, 2013. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

▲Up To Search▲

Price & Availability of CY2X0137FLXCT

	To Download CY2X0137FLXCT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .